1. Field of the Invention
This invention relates to chopper stabilized amplifiers, and more particularly to chopper stabilized operational amplifier circuits which seek to reduce input voltage offset and noise.
2. Description of the Prior Art
Offset voltage drift has been a problem in designing circuits with operational amplifiers (op amps). The input offset voltage can generally be adjusted to a very low value with the help of an external potentiometer or selected fixed resistors, but this adjustment is good only for the ambient temperature and point in time at which it was made. With a few degrees of change in temperature or after a few months, the offset voltage may again become a problem.
Offset voltage stabilization has been accomplished by adding an auxiliary direct current (DC) amplifier to the main amplifier. The auxiliary amplifier alternately nulls its own offset and the offset of the main amplifier. The auxiliary amplifier is not responsible for amplifying the main signal and needs only a limited frequency response. Chopper-stabilized op amps are well-known and are discussed, for example, in Jones and Webb, "Chopper-stabilized op amp combines MOS and bipolar elements on one chip", Electronics, Sep. 27, 1973, pages 209-213. FIG. 1 shows the basic approach. A1 is the main amplifier, and A2 is the auxiliary amplifier. If A2 has a large gain, the effective input offset voltage of the entire circuit will be nearly equal to that of A2 by itself. This is because the input offset voltage of A1 is divided by the gain of A2 in establishing its contribution to the offset of the entire circuit. The open-loop DC gain of the overall circuit is the product of the gains of A1 and A2.
A more detailed version of the basic chopper-stabilized amplifier circuit of FIG. 1 is provided in FIG. 2a. The main amplifier is op amp A4, while the auxiliary amplifier is op amp A5. The circuit is driven by a clock circuit 4 which alternates its output between output lines 6 and 8 at a constant frequency; when the output on line 6 is high the output on line 8 is low, and vice versa. The circuit thus has two phases, with .phi.1 including the first phase when the output on line 6 is high, and .phi.2 the second phase when the output on line 8 is high.
The inverting inputs to A4 and A5 are connected through a switch S3 that is closed during .phi.1, while the inverting and non-inverting inputs of A5 are connected through a separate switch S4 that is closed during .phi.2. The input signal at terminal 10 is applied in common to the non-inverting inputs of A4 and A5. A pair of resistors R3 and R4 are connected in a feedback circuit for A4 to establish its gain. The output of auxiliary amplifier A5 is connected to the nulling input of A4 through a .phi.1 switch S5, and to the nulling input of A5 through a .phi.2 switch S6; holding capacitors C4 and C5 are connected to the nulling inputs of A4 and A5, respectively.
The chopper-stabilized amplifier circuit of FIG. 2a seeks to minimize the input offset voltage. The .phi.1 and .phi.2 switch control signals are illustrated in FIG. 2b; while one is high the other is low, and vice versa. During .phi.1 the circuit's open loop gain is (1+A5)A4, while during .phi.2 the circuit's open lop gain is equal to the gain of A4 by itself. The input offset voltage for A4 is equal to the different between the voltages across C4 and C5 divided by A5; minimizing this voltage difference minimizes the offset voltage.
In operation, the inputs of A5 are shorted together during .phi.2, and the output of A5 drives its nulling input via switch S6 in a negative feedback connection that stabilizes the nulling voltage across C5 and the A5 output. During .phi.1, A5 drives the nulling input to A4 via switch S5, adjusting the output of A4 so that the entire A4/A5 loop is stabilized. If the voltages across C4 and C5 are equal when the A4/A5 loop has stabilized, then there is zero voltage across the inverting and non-inverting inputs of A4, which corresponds to a zero input voltage offset.
An equivalent circuit for the described chopper-stabilized amplifier is given in FIG. 3. Two gain amplifiers G1 and G2 are shown. The gain of G1 is equal to that of A4; the gain of G2 is equal to (1+A5)A4. G1 is connected between the input and output terminals, and G2 is disconnected, during .phi.2. G2 is then switched in and G1 switched out during .phi.1.
A problem with this type of switching between two different gain conditions is that it introduces intermodulation distortion (IMD) between the signal and the clock frequency at which switching takes place. IMD occurs at the various sums and differences of the harmonics of the two signals, and the clock itself can introduce noise. This situation is illustrated in FIG. 4. The input signal frequency is F.sub.S, while the clock frequency is f.sub.CLK. For f.sub.S &gt;F.sub.CLK /2, IMD noise spikes will be present at levels substantially above the normal noise floor. The magnitude of the IMD spikes is greatest for lower order harmonics, and generally decreases for higher order harmonics. In addition, the switch operation will normally not be perfect, and charge will be injected into the amplifiers when they are turned off, producing both a clock noise at the switch frequency f.sub.CLK, and an increased voltage offset.
The conventional approach to overcoming these problems is to try to make the clock frequency as high as possible. However, the amplifiers are relatively slow and take time to settle to a low voltage offset level. Depending upon the particular circuit, the input offset voltage rises rapidly above a threshold clock frequency, which is typically on the order of 1-10 KHz, as illustrated in FIG. 5. This imposes a substantial limitation upon the circuit's effective bandwidth.